1. Technical Field
The present disclosure relates to a configurable I2C interface and, more particularly, to the input/output buffers of devices connected on the I2C bus, which can switch in three different modes of operation (Standard/Fast/High-Speed).
2. Description of the Related Art
The I2C bus is a two-wire communication bus that is used for synchronous serial data transfer. The I2C bus can transfer data at rates up to 100 kbit/s (standard mode), 400 kbit/s (fast mode), or 3.4 Mbit/s (high-speed mode). The load on the I2C bus can also vary from 10 pf to 400 pf. In standard and fast mode it is easy to achieve the required data rate without altering the system design. However, when the I2C bus switches into high-speed mode, the IO's used for the standard and fast mode fail to achieve the required data rate. It therefore becomes necessary to provide additional circuitry to enable the IO's to achieve the required data rate.
The available literature describes a technique for achieving the high speed data rate using an internal current source when the load on the bus is up to 100 pf, and using a combination of internal and external current sources when the load on the I2C bus is more than 100 pf. This technique is useful when the load on the I2C bus and its mode of operation (data rate) is fixed.
FIG. 1 shows the system level architecture of an implementation of an I2C driver implemented according to a prior design when the bus is operating in high speed mode and the load on the bus is higher than 100 pf. Here, an external current source is connected to a serial data line and a serial clock line each. These external current sources help to achieve the required rise and fall times of the I2C bus. However, when the load on the I2C bus becomes less than 100 pf, these external current sources must be removed. This arrangement complicates the switching of the bus from one mode to another.
FIG. 2 shows the structure of an I2C system according to another prior design (when the bus is in a high speed mode and the load on the I2C bus is higher than 100 pf) when operating with two different bus supply voltages. Each time the supply voltage on the I2C bus changes, additional current sources on the I2C bus must be connected for achieving the required data rate. This requirement makes the design of the I2C system very complex.